1. Field of the Invention
The present invention generally relates to a semiconductor memory device having a sense amplifier and a method for overdriving the sense amplifier, and more specifically, to a semiconductor memory device having a sense amplifier and a method for overdriving the sense amplifier for effectively amplifying data of a bitline, thereby improving output time of data and reducing a precharge time.
2. Description of the Prior Art
FIG. 1 is a block diagram illustrating a general semiconductor memory device.
The conventional semiconductor memory device comprises a memory block 1 including a plurality of memory cell arrays and a control block 2 for storing data in the memory block 1 and outputting the data stored in the memory block 1.
The memory block 1 comprises a plurality of memory cell arrays 3a and 3b each including a plurality of memory cells, and sense amplifier arrays 4 including a plurality of sense amplifiers for amplifying data stored in the memory cells.
The control block 2 comprises a row controller 5 for selecting a wordline, a column controller 6 for selecting a bitline, and an output unit 7 for outputting data.
To improve integrity of the semiconductor memory device, one sense amplifier array 4 is arranged between the two memory cell arrays 3a and 3b. The sense amplifier array 4 is connected to the selected memory cell array 3a in response to a previously set connection signal.
FIG. 2 is a block diagram illustrating the sense amplifier array 4 of FIG. 1.
The sense amplifier array 4 comprises a plurality of sense amplification unit 8. Each sense amplification unit 8 comprises a sense amplifier 9, a data output unit 10, a precharge unit 11, switch units 12a and 12b and equalization unit 13a and 13b. The data output unit 10 outputs data amplified by the sense amplifier 9 into a data bus DB. The precharge unit 11 precharges and equalizes bitlines BLs and /BLs of the sense amplifier array 4. The switch units 12a and 12b selectively connects the sense amplifier 9 to the selected memory cell arrays 3a and 3b. The equalization unit 13a and 13b equalizes bitlines Bla, /BLa and BLb, /BLb in the memory cell arrays 3a and 3b, respectively.
The sense amplifier array 4 comprises a sense amplifier controller 14 for selectively driving the sense amplifier 9, and a switch controller 15 for controlling the switch units 12a and 12b. Here, the sense amplifier 9 has a latch type.
The data output unit 10, which is controlled by a column selecting signal YI outputted from the column controller 6, transmits data amplified by the sense amplifier 9 into the data bus DB.
The precharge unit 11, which is controlled by a bitline equalization signal BLEQ, precharges and equalizes bitlines BLs and /BLs of the sense amplifier array 4 to a bitline precharge voltage VBLP.
The equalization units 13a and 13b, which are controlled by bitline equalization signals BLEQH and BLEQL, equalizes the bitlines BLa, /BLa and BLb, /BLb of the corresponding memory cell arrays 3a and 3b, respectively.
The sense amplifier controller 14 generates control signals RTO and /S to selectively activate the sense amplifier 9.
The switch controller 15 generates connection signals BISH and BISL to selectively connect the sense amplifier array 4 to the selected memory cell arrays 3a and 3b, respectively.
A capacitor C represents load capacitance generated in each bitline.
FIG. 3 is a circuit diagram illustrating the switch controller 15 of FIG. 2. Here, FIG. 3 shows a part of the switch controller 15 for generating the connection signal BISH to selectively connect the sense amplifier array 4 to the memory cell array 3a. Since the other part of the switch controller 15 for generating the connection signal BISL has the same structure as that for generating the connection signal BISH, the explanation is omitted.
The switch controller 15 comprises a precharge unit 16, a signal generator 17 and an inactivation unit 18. The precharge unit 16 precharges an output terminal BISH to a high level VDD. The signal generator 17 sets the output terminal BISH to a high potential level VPP. The inactivation unit 18 sets the output terminal BISH to a low level VSS.
The high level VDD is a power voltage level used in a common semiconductor memory device. The high potential level VPP is used when a high voltage level is required in a voltage applied to a wordline or a bitline equalization signal, and is an internal power voltage higher than the power voltage VDD. For example, when the power voltage VDD is 2.5V, the high potential power voltage VPP is 3.4V.
The precharge unit 16 comprises an inverter INV1, a level shifter 19 and a PMOS transistor PM1. The inverter INV1 inverts a control signal BLKCOM for precharging the output terminal BISH to the power voltage VDD. The level shifter 19 shifts an output signal from the inverter INV1 to the high potential voltage VPP. The PMOS transistor PM1 precharges the output terminal BISH to the power voltage VDD in response to an output signal from the level shifter 19.
The signal generator 17 comprises an inverter INV2, an NOR gate NR1, an NAND gate ND1, a level shifter 20 and a PMOS transistor PM2. The inverter INV2 inverts a control signal BLKNEXT. The NOR gate NR1 performs an NOR operation on an output signal from the inverter INV2 and a separation control signal BISOFF. The NAND gate ND1 performs an NAND operation on an output signal from the NOR gate NR1 and a control signal BLKSELF. The level shifter 20 shifts an output signal from the NAND gate ND1 to a low potential voltage VBB. The PMOS transistor PM2 sets the output terminal BISH to the high potential voltage VPP in response to an output signal from the level shifter 20.
Since a source of the PMOS transistor PM2 receives the high potential voltage VPP, a gate of the PMOS transistor PM2 receives the high potential voltage VPP other than the power voltage VDD using the level shifter 20. As a result, since the connection signal BISH is not precharged into the power voltage VDD, the mis-operation can be prevented.
The inactivation unit 18 comprises an inverter INV3, an NAND gate ND2 and an NMOS transistor NM1. The inverter INV3 inverts the control signal BLKNEXT. The NAND gate ND2 performs an NAND operation on an output signal from the inverter INV3 and the separation control signal BISOFF. The NMOS transistor NM1 sets the output terminal BISH to a low level-VSS in response to an output signal from the NAND gate ND2.
FIG. 4 is a circuit diagram illustrating an example of the level shifter 19 of FIG. 3. Since the level shifter 20 of the signal generator 17 has the same structure as that of the level shifter 19, the explanation of the level shifter 20 is omitted.
The level shifter 19 comprises PMOS transistors PM3 and PM4, an inverter INV4 and NMOS transistors NM2 and NM3. The cross-coupled PMOS transistors PM3 and PM4 have a common source to receive the high potential voltage VPP. The NMOS transistor NM2 has a drain connected to that of the PMOS transistor PM3, a source to receive the ground voltage VSS, and a gate to receive an output signal IN from the inverter INV1. The inverter INV4 inverts the signal IN. The NMOS transistor NM3 has a drain connected to that of the PMOS transistor PM2, a source to receive the ground voltage VSS, and a gate to receive the output signal from the inverter INV4. An output signal OUT is outputted from a common drain of the PMOS transistor PM4 and the NMOS transistor NM3.
If the output signal IN from the inverter INV1 is at a high level, the NMOS transistor NM2 and the PMOS transistor PM4 are turned on. As a result, the output signal OUT becomes at the high potential level VPP. If the output signal IN from the inverter INV1 is at a low level, the NMOS transistor NM3 and the PMOS transistor PM3 are turned on. As a result, the output signal OUT becomes the ground voltage VSS.
FIG. 5 is a timing diagram illustrating the operation of the switch controller 15 of FIG. 3.
In a precharge interval a, the control signal BLKCOM for controlling the precharge operation of the connection signals BISH and BISL becomes at a high level, and the other signals BLKSELF and BLKNEXT become at a low level. AS a result, the connection signals BISH and BISL are precharged to the power voltage VDD.
The connection signals BISH and BISL are precharged in order to help rapid separation and connection of the sense amplifier array 4 with the memory cell arrays 3a and 3b. 
In a connection interval b, the control signal BLKCOM for controlling the precharge operation becomes at a low level, and the other signals BLKSELF and BLKNEXT become at a high level. As a result, the upper connection signal BISH for connecting the sense amplifier array 4 to the selected memory cell array 3a becomes at the high potential level VPP, and the lower connection signal BISL becomes at the low level VSS.
The control signals BLKCOM, BLKNEXT and BLKSELF are timing signals for generating the connection signals BISH and BISL using a row address.
The control signal BLKCOM is a timing signal for connecting the memory cell arrays 3a and 3b adjacent to the sense amplifier array 4. The control signal BLKSELF is a timing signal for connecting the sense amplifier array 4 to the selected memory cell array 3a. The control signal BLKNEXT is a timing signal for separating the sense amplifier array 4 from the unselected memory cell array 3b. 
The separation control signal BISOFF is a timing signal for temporarily separating the sense amplifier array 4 from the selected memory cell array 3a. 
After the sense amplifier array 4 is connected to the selected memory cell array 3a, a wordline of the selected memory cell array 3a corresponding to an inputted rwo address is selected. If the selected wordline is activated, data stored in the memory cell connected to the selected wordline is transmitted into the bitline BLa.
Thereafter, the sense amplifier control signals RTO and /S are activated, and the sense amplifier 9 senses and amplifies data on the bitline BLs. Here, the control signal BISOFF for temporarily separating the sense amplifier array 4 from the selected memory cell array 3a is inputted with a pulse type, and the connection signal BISH becomes at a low level temporarily for a high pulse interval c.
As a result, the sense amplifier array 4 is temporarily separated from the selected memory cell array 3a. 
Here, since large load capacitance C in the bitline BLs and /BLs decreases, the sense and amplification operations of the sense amplifier 9 can be rapidly performed.
Next, in a connection interval d, the connection signal BISH becomes at a high level, and the sense amplifier array 4 is connected to the selected memory cell array 3a again.
Here, the column selecting signal YI corresponding to the inputted column address is generated to transmit data on the bitline BLs into the data bus DB.
FIG. 6 is a circuit diagram illustrating the sense amplifier controller 14 of FIG. 2.
The sense amplifier controller 14 comprises a precharge unit 21, a PMOS transistor PM5 and an NMOS transistor NM4. The precharge unit 21 precharges and equalizes the control signals RTO and /S to a bitline precharge voltage VBLP in response to the equalization signal BLEQ. The PMOS transistor PM5 pulls up the high level signal RTO to a core voltage VCORE in response to a pull-up control signal /RTOE. The NMOS transistor NM4 pulls down the low level signal /S to the low level VSS in response to a pull-down control signal SZE.
FIGS. 7a and 7b are timing diagrams illustrating the operation of the semiconductor memory device of FIGS. 1 and 2. Here, data stored in the memory cell has a low level.
FIG. 7a is a timing diagram illustrating the operation of the general semiconductor memory device.
When the upper connection signal BISH as the high level VPP and the lower connection signal BISL as the low level VSS are outputted from the switch controller 15, the sense amplifier 9 is connected to the upper memory cell array 3a and separated from the lower memory cell array 3b. 
If a wordline of the upper memory cell array 3a is selected and the high level VPP is applied, data stored in the memory cell connected to the selected wordline is loaded in the precharged bitline BLa.
The sense amplifier 9 of the sense amplifier array 4, which is activated by the control signals RTO and /S, senses and amplifies data on the bitline BLs.
The data output unit 10 outputs the amplified data of the bitline BLs corresponding to the column selecting signal YI outputted from the column controller 6 into the data bus DB.
The column controller 6 activates the column selecting signal YI corresponding to the inputted column address.
As a semiconductor memory device becomes higher integrated, one memory cell array 3a or 3b comprises more unit memory cells. As a result, the load capacitance C of the bitline increases.
The sense amplifier 9 requires more time to sense and amplify data of the bitline BLs, which results in delay of the column selecting operation.
Since the timing when the sense amplifier 9 amplifies data on the bitline BLs affects the operation time of the semiconductor memory device, it is importance to minimize the amplification time.
In order to reduce the amplification time of the sense amplifier 9, load capacitance C is reduced.
FIG. 7b is a timing diagram illustrating the operation of the conventional semiconductor memory device when the bitline is separated at the initial stage of the amplification operation to reduce the amplification time of the sense amplifier 9.
After the data stored in the memory cell is loaded in the bitline Bla and BLs, the sense amplifier array 4 is separated from the selected memory cell array 3a before the sense amplifier 9 senses and amplifies the data of the bitline BLs, thereby reducing the load capacitance C of the bitline BLa. As a result, the amplification time of the sense amplifier 9 is reduced.
The connection signal BISH for selectively separating the sense amplifier array 4 from the selected upper memory cell array 3a is set at the low level VSS when the sense amplifier 9 is activated.
The sensing and amplifying operation of the sense amplifier 9 is more rapidly performed when the sense amplifier array 4 is temporarily separated from the selected memory cell array 3a than when the sense amplifier array 4 is not temporarily separated from the selected memory cell array 3a. 
As a result, the operation speed of the semiconductor memory device can be improved. A parameter tRCD (Row address to Column address Delay) representing delay time from a row address input to a column address input is improved.
However, as shown in FIG. 7b, the voltage level of the bitline /BLs has a large jitter when the connection signal BISH becomes at a low level temporarily and then transits to a high level.
Additionally, it takes much time to stabilize the bitline voltage due to large load capacitance C of the bitline BLa of the memory cell array 3a. 
As a result, since the precharge timing of the bitline is delayed due to restoration time of data in the memory cell, the parameter tRCD is degraded.